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CY7C1303CV25 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C1303CV25
Description  18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1303CV25 Datasheet(HTML) 5 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1303CV25
CY7C1306CV25
Document #: 001-44701 Rev. *B
Page 5 of 21
TDO
Output
TDO for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
N/A
Not Connected to the Die. Can be tied to any voltage level.
GND/72M
Input
Address expansion for 72M. This pin must be tied to GND on CY7C1303CV25.
NC/72M
N/A
Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306CV25.
GND/144M
Input
Address expansion for 144M. This pin must be tied to GND on CY7C1303CV25/CY7C1306CV25.
GND/288M
Input
Address expansion for 288M. This pin must be tied to GND on CY7C1306CV25.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and
AC measurement points.
VDD
Power Supply Power Supply Inputs to the Core of the Device.
VSS
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
[+] Feedback


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