6 / 14 page
CY7C199CN
Document #: 001-06435 Rev. *B
Page 6 of 14
AC Electrical Characteristics [4]
Parameter
Description
–12
–15
–20
–25
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tRC
Read Cycle Time
12
–
15
–
20
–
25
–
ns
tAA
Address to Data Valid
–
12
–
15
–
20
–
25
ns
tOHA
Data Hold from Address
Change
3
–
3
–
3
–
3
–
ns
tACE
CE to Data Valid
–
12
–
15
–
20
–
25
ns
tDOE
OE to Data Valid Ind’l/Com’l
–
5
–
7
–
9
–
9
ns
Automotive-A
–
6
–
–
–
–
–
–
tLZOE
OE to Low-Z [5]
0
–
0
–
0
–
0
–
ns
tHZOE
OE to High-Z [5, 6]
–
5
–
7
–
9
–
9
ns
tLZCE
CE to Low-Z [5]
3
–
3
–
3
–
3
–
ns
tHZCE
CE to High-Z [5, 6]
–
5
–
7
–
9
–
9
ns
tPU
CE to Power Up
0
–
0
–
0
–
0
–
ns
tPD
CE to Power Down
–
12
–
15
–
20
–
20
ns
tWC
Write Cycle Time [7]
12
–
15
–
20
–
25
–
ns
tSCE
CE to Write End
9
–
10
–
15
–
15
–
ns
tAW
Address Setup to Write End
9
–
10
–
15
–
15
–
ns
tHA
Address Hold from Write End
0
–
0
–
0
–
0
–
ns
tSA
Address Setup to Write Start
0
–
0
–
0
–
0
–
ns
tPWE
WE Pulse Width
8
–
9
–
15
–
15
–
ns
tSD
Data Setup to Write End
8
–
9
–
10
–
10
–
ns
tHD
Data Hold from Write End
0
–
0
–
0
–
0
–
ns
tHZWE
WE LOW to High-Z [5, 6]
–
7
–
7
–
10
–
10
ns
tLZWE
WE HIGH to Low-Z [5]
3
–
3
–
3
–
3
–
ns
Data Retention Characteristics [8]
Parameter
Description
Condition
Min
Max
Unit
VDR
VCC for Data Retention
2.0
–
V
ICCDR
Data Retention Current
VCC = VDR = 2.0V, CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
–
150
µA
tCDR
Chip Deselect to Data
Retention Time
0
–
ns
tR
Operation Recovery Time
200
–
µs
Notes
4. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZCE, tHZWE are specified as in part (b) of the “” on page 1. Transitions are measured ± 200 mV from steady state voltage.
7. The internal memory write time is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write.
8. L-version only.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
