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KAD5612P-17Q72 Datasheet(PDF) 3 Page - Intersil Corporation |
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KAD5612P-17Q72 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 28 page 3 FN6803.1 January 21, 2009 Table of Contents Absolute Maximum Ratings ......................................... 4 Thermal Information...................................................... 4 Electrical Specifications ............................................... 4 Digital Specifications .................................................... 6 Timing Diagrams ........................................................... 6 Switching Specifications .............................................. 7 Pinout/Package Information......................................... 8 Pin Descriptions.......................................................... 8 Pinout ......................................................................... 9 Typical Performance Curves ........................................ 10 Theory of Operation ...................................................... 13 Functional Description ................................................ 13 Power-On Calibration ................................................. 13 User-Initiated Reset.................................................... 14 Analog Input ............................................................... 14 Clock Input ................................................................. 15 Jitter............................................................................ 16 Voltage Reference...................................................... 16 Digital Outputs ............................................................ 16 Over Range Indicator ................................................. 16 Power Dissipation....................................................... 16 Nap/Sleep................................................................... 16 Data Format ............................................................... 17 Serial Peripheral Interface ........................................... 18 SPI Physical Interface................................................ 18 SPI Configuration....................................................... 19 Device Information ..................................................... 20 Indexed Device Configuration/Control ....................... 20 Global Device Configuration/Control.......................... 21 Device Test ................................................................ 22 SPI Memory Map ....................................................... 23 Equivalent Circuits ....................................................... 24 Layout Considerations ................................................. 25 Split Ground and Power Planes ................................. 25 Clock Input Considerations ........................................ 25 Exposed Paddle......................................................... 25 Bypass and Filtering .................................................. 25 LVDS Outputs ............................................................ 25 LVCMOS Outputs ...................................................... 25 Unused Inputs............................................................ 25 Definitions ..................................................................... 26 Revision History ........................................................... 27 Package Outline Drawing............................................. 28 L72.10x10D................................................................ 28 KAD5612P |
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