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KAD5512HP-17Q72 Datasheet(PDF) 8 Page - Intersil Corporation |
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KAD5512HP-17Q72 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 32 page 8 FN6808.2 March 4, 2009 Latency (Pipeline Delay) L 8.5 cycles Overvoltage Recovery tOVR 1cycles SPI INTERFACE (Notes 7, 8) SCLK Period Write Operation t CLK 64 ns Read Operation tCLK 264 ns SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) Read or Write 25 50 75 % SCLK ↑ to CSB↓ Setup Time Read or Write tS -4 ns SCLK ↑ to CSB↑ Hold Time Read or Write tH -12 ns SCLK ↑ to Data Setup Time Read or Write tDS -4 ns SCLK ↑ to Data Hold Time Read or Write tDH -12 ns NOTES: 7. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. 8. The SPI may operate asynchronously with respect to the ADC sample clock. 9. The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. Switching Specifications (Continued) PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS KAD5512HP |
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