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CY7B991.5JIT Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7B991.5JIT
Description  Programmable Skew Clock Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B991.5JIT Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7B991
CY7B992
Document Number: 38-07138 Rev. *B
Page 6 of 19
Electrical Characteristics
Over the Operating Range[6]
CY7B991
CY7B992
Parameter
Description
Test Conditions
Min
Max
Min
Max
Unit
VOH
Output HIGH Voltage
VCC = Min IOH = –16 mA
2.4
V
VCC = Min, IOH =–40 mA
VCC–0.75
VOL
Output LOW Voltage
VCC = Min, IOL = 46 mA
0.45
V
VCC = Min, IOL = 46 mA
0.45
VIH
Input HIGH Voltage
(REF and FB inputs only)
2.0
VCC
VCC
1.35
VCC
V
VIL
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
V
VIHH
Three Level Input HIGH
Voltage (Test, FS, xFn)[10]
Min
≤ V
CC ≤ Max
VCC – 0.85
VCC
VCC – 0.85
VCC
V
VIMM
Three Level Input MID
Voltage (Test, FS, xFn)[10]
Min
≤ V
CC ≤ Max
VCC/2 –
500 mV
VCC/2 +
500 mV
VCC/2 –
500 mV
VCC/2 +
500 mV
V
VILL
Three Level Input LOW
Voltage (Test, FS, xFn)[10]
Min
≤ V
CC
Maximum
0.0
0.85
0.0
0.85
V
IIH
Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = Max.
10
10
μA
IIL
Input LOW Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = 0.4V
–500
–500
μA
IIHH
Input HIGH Current
(Test, FS, xFn)
VIN = VCC
200
200
μA
IIMM
Input MID Current
(Test, FS, xFn)
VIN = VCC/2
–50
50
–50
50
μA
IILL
Input LOW Current
(Test, FS, xFn)
VIN = GND
–200
–200
μA
IOS
Output Short Circuit
Current[8]
VCC = Max, VOUT
= GND (25
°C only)
–250
N/A
mA
ICCQ
Operating Current Used by
Internal Circuitry
VCCN=VCCQ=Max,
All Input
Selects Open
Com’l
85
85
mA
Mil/Ind
90
90
ICCN
Output Buffer Current per
Output Pair[9]
VCCN = VCCQ = Max,
IOUT = 0 mA
Input Selects Open, fMAX
14
19
mA
PD
Power Dissipation per
Output Pair[10]
VCCN = VCCQ = Max,
IOUT = 0 mA
Input Selects Open, fMAX
78
104[11]
mW
Notes
6. For more information see “Group A Subgroup Testing” on page 17.
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all datasheet limits are achieved.
8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must
not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pairis approximated by the following expression that includes device current plus load current:
CY7B991:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992:
ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F
< C.
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.


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