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PRELIMINARY
CY2XF33
Document Number: 001-53148 Rev. *A
Page 4 of 7
Termination Circuits
Figure 2. LVDS Termination
AC Electrical Characteristics[4]
Parameter
Description
Condition
Min
Typ
Max
Unit
FOUT
Output Frequency[6]
50
–
690
MHz
FSC
Frequency Stability, commercial
devices[5]
TA = 0°C to 70°C
–
–
±35
ppm
FSI
Frequency Stability, industrial
devices[5]
TA = –40° to 85°C
–
–
±55
ppm
AG
Aging, 10 years
–
–
±15
ppm
TDC
Output Duty Cycle
F <= 450 MHz, measured at zero crossing
45
50
55
%
F > 450 MHz, measured at zero crossing
40
50
60
%
TR, TF
Output Rise and Fall Time
20% and 80% of full output swing
–
350
–
ps
TLOCK
Startup Time
Time for CLK to reach valid frequency
measured from the time VDD = VDD(min)
––
10
ms
TLFS
Re-lock Time
Time for CLK to reach valid frequency from
FS0 or FS1 pin change
––
10
ms
TJitter(φ)
RMS Phase Jitter (Random)
fOUT = 106.25 MHz (12 kHz–20 MHz)
–
1
–
ps
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
6. This parameter is specified in CyberClocks Online software.
CLK
CLK#
100
Ω
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