5

FN6442.1

September 29, 2008

RAMP

RAMP Sink Current Device Impedance

-

-

20

Ω

RAMP to PWM Comparator Offset

65

80

95

mV

Bias Current

-5.0

-

-2.0

µA

PULSE WIDTH MODULATOR

Minimum Duty Cycle

VERR < 0.6V

-

-

0

%

Maximum Duty Cycle (per half-cycle)

-

94

-

%

RTD = 2.00k

Ω, CT = 220pF

-

97

-

%

RTD = 2.00k

Ω, CT = 470pF

-

99

-

%

Zero Duty Cycle VERR Voltage

0.85

-

1.20

V

VERR to PWM Comparator Input Offset

0.7

0.8

0.9

V

VERR to PWM Comparator Input Gain

0.31

0.33

0.35

V/V

Common Mode (CM) Input Range

(Note 4)

0

-

V

ERROR AMPLIFIERS

Input Common Mode (CM) Range

(Note 4)

0

-

VREF

V

GBWP

(Note 4)

5

-

-

MHz

VERR VOL

-

-

0.4

V

VERR VOH

4.20

-

-

V

VERR Pull-Up Current Source

VERR = 2.5V

0.8

1.0

1.3

mA

EA Reference

0.594

0.600

0.606

V

EA Reference + EA Input Offset Voltage

0.590

0.600

0.612

V

OSCILLATOR

Frequency Accuracy, Overall

(Note 4)

165

183

201

kHz

-10

-

+10

%

Frequency Variation with VDD

-0.3

1.7

%

Temperature Stability

-4.5

-

%

(Note 4)

-1.5

-

%

Charge Current

-193

-200

-207

µA

Discharge Current Gain

19

20

23

µA/µA

CT Valley Voltage

Static Threshold

0.75

0.80

0.88

V

CT Peak Voltage

Static Threshold

2.75

2.80

2.88

V

CT Pk-Pk Voltage

Static Value

1.92

2.00

2.05

V

RTD Voltage

1.97

2.00

2.03

V

RESDEL Voltage Range

0-

2

V

1.95

2.0

2.05

V/V

Electrical Specifications

Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

Temperature limits established by characterization and are not production tested. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ISL6755