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 TI
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5 page 
DEVICE INFORMATION Thermal Shutdown Current Limit UVLO Bandgap IN EN OUT BIAS PIN CONFIGURATION IN GND BIAS 6 5 4 OUT NC EN 1 2 3 Thermal Pad (1) BIAS IN EN GND OUT C3 B2 A3 C1 A1 TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 Functional Block Diagram DRV PACKAGE YZU PACKAGE SON-6 WCSP-5 (TOP VIEW) (TOP VIEW) (1) It is recommended that the SON (DRV) package thermal pad be connected to ground. PIN DESCRIPTIONS TPS720xx NAME DRV YZU DESCRIPTION Output pin. A 2.2 µF ceramic capacitor is connected from this pin to ground, for stability and to provide load OUT 1 A3 transients. See Input and Output Capacitor Requirements in the Application Information section. NC 2 — No connection. Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A EN 3 C3 logic low on this pin turns off the device. Bias supply pin. It is recommended that this input be bypassed with a ceramic capacitor to ground for better BIAS 4 C1 transient performance. See Input and Output Capacitor Requirements in the Application Information section. GND 5 B2 Ground pin. Input pin. This pin can be a maximum of 4.5V; VIN must not exceed VBIAS. Bypass this input with a ceramic IN 6 A1 capacitor to ground. See Input and Output Capacitor Requirements in the Application Information section. Copyright © 2008–2009, Texas Instruments Incorporated 5 |
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