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Starting TPS6507x SLVS950 – JULY 2009 ....................................................................................................................................................................................................... www.ti.com Table 9. Sequencing Settings (continued) DEDICATED DCDC_SQ[2..0] LDO_SQ[2..0] COMMENT FOR TPS65072(1) Sirf Atlas 4 111 010 DCDC1=VDDIO (3.3V) DCDC2=VMEM (1.8V) DCDC3= VDD_PDN (1.2V) driven by X_PWR_EN LDO1=VDD_PLL (1.2V) LDO2=VDD_PRE (1.2V) EN_EXTLDO=VDDIO_RTC PGOOD delay time (reset delay): 20ms <PGOODMASK>=10h: reset based on VDCDC1 TPS65073 OMAP3503 101 001 Supporting SYS-OFF mode: OMAP3515 Supporting DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS, OMAP3525 SYS-OFF mode VDDS_SRAM (1.8V) OMAP3530 DCDC2=VDDCORE (1.2V) DCDC3=VDD_MPU_IVA (1.2V) LDO1= VDDS_DPLL_DLL, VDDS_DPLL_PER (1.8V) LDO2=VDDS_MMC1 (1.8V) PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Ch: based on VDCDC1, VDCDC2, VDCDC3 TPS650731 OMAP35xx 110 011 DCDC1=VDDS_WKUP_BG, VDDS_MEM, VDDS, VDDS_SRAM (1.8V) DCDC2=VDDCORE (1.2V) DCDC3=VDD_MPU_IVA (1.2V) LDO1=VDDS_DPLL_DLL (1.8V) LDO2=VDDA_DAC (1.8V): OFF, enabled by I2C PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 TPS650732 OMAP3505 110 001 DCDC1=VDDS1-5 (1.8V) OMAP3517 DCDC2=VDDSHV (3.3V) DCDC3=VDD_CORE (1.2V) LDO1=VDDA1P8V (1.8V) LDO2=VDDS_DPLL (1.8V) PGOOD delay time (reset delay): 400ms <PGOODMASK>=1Ch: reset based on VDCDC1, VDCDC2, VDCDC3 (1) Product Preview TPS6507x was developed for battery powered applications with focus on lowest shutdown and quiescent current. In order to achieve this, in shutdown all mayor blocks and the system voltage at the output of the power path (SYS) are turned off and only the input that turns on TPS6507x, pin PB_IN, is supervised. TPS6507x is designed such that only an ON-key on PB_IN is needed pulling this pin LOW to enable TPS6507x. No external pull-up is needed as this is integrated into TPS6507x. Once PB_IN is pulled LOW, the system voltage is ramped and the dcdc converters and LDOs are started with the sequencing defined for the version used. If PB_IN is released again, TPS6507x would turn off, so a pin was introduced to keep TPS6507x enabled after PB_IN was released. Pin POWER_ON serves this function and needs to be pulled HIGH before the user releases the ON-key (PB_IN = HIGH). This HIGH signal at POWER_ON can be provided by the GPIO of a processor or by a pull-up resistor to any voltage in the system which is higher than 1.2V. Pulling POWER-ON to a supply voltage would significantly reduce the time PB_IN has to be asserted LOW. If POWER_ON is tied to a GPIO, the processor has to boot up first which may take some time. In this case however, the processor could do some additional debouncing, hence does not keep the power enabled if the ON-key is only pressed for a short time. When there is a supply voltage for the battery charger at pins AC or USB, the situation is slightly different. In this case, the power path is enabled and the system voltage (SYS) has ramped already to whatever the voltage at AC or USB is. The dcdc converters are not enabled yet but the start-up could not only be done by pulling PB_IN=LOW but also by pulling POWER_ON=HIGH. 70 Copyright © 2009, Texas Instruments Incorporated |
