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TPS51217 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS51217 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 27 page DEVICE INFORMATION 1 2 3 4 5 10 9 8 7 6 PGOOD TRIP EN VFB TRAN VBST DRVH SW V5IN DRVL GND DSCPACKAGE (TOP VIEW) TPS51217DSC (TRIP) OCL V V 8 = TPS51217 www.ti.com ...................................................................................................................................................................................................... SLUS947 – JUNE 2009 Thermal pad is used as an active terminal of GND. PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is DRVH 9 O defined by the voltage across VBST to SW node bootstrap flying capacitor Synchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined by DRVL 6 O V5IN voltage. EN 3 I SMPS enable pin. Short to GND to disable the device. Thermal GND I Ground Pad Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signal PGOOD 1 O voltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes within specified limits. Power bad, or the terminal goes low, after a 2- µs delay. Switch node. A high-side MOSFET gate drive return. Also used for on time generation and output SW 8 I discharge. Dynamic voltage change control. It forces CCM and masks PGOOD, OVP and UVP when this pin's status is pulled up or pulled down. The masking is terminated 900 µs after TRAN pin voltage returns to normal. TRAN 5 I See the DYNAMIC VOLTAGE STEP and PGOOD/OVP/UVP MASK section for a detailed description. Leave this pin open when dynamic voltage change is not used. OCL detection threshold setting pin. 10 µA at room temperature, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows. TRIP 2 I (0.2 V ≤ V(TRIP) ≤ 3 V) V5IN 7 I 5 V +30% / –10% power supply input. Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin to VBST 10 I the SW pin. Internally connected to V5IN via bootstrap MOSFET switch. VFB 4 I SMPS feedback input. Connect the feedback resistor divider. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS51217 |
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