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SN75LVDS83BDGGR Datasheet(PDF) 9 Page - Texas Instruments |
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SN75LVDS83BDGGR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 28 page ELECTRICAL CHARACTERISTICS SN75LVDS83B www.ti.com ........................................................................................................................................................................................................ SLLS846 – MAY 2009 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VT Input voltage threshold IOVCC/2 V Differential steady-state output voltage mV |VOD| 250 450 magnitude RL = 100Ω, See Figure 4 Change in the steady-state differential Δ|VOD| output voltage magnitude between 1 35 mV opposite binary states Steady-state common-mode output VOC(SS) 1.125 1.375 V voltage Peak-to-peak common-mode output See Figure 4 VOC(PP) 35 mV voltage tR/F (Dx, CLKin) = 1ns IIH High-level input current VIH = IOVCC 25 µA IIL Low-level input current VIL = 0 V ±10 µA VOY = 0 V ±24 mA IOS Short-circuit output current VOD = 0 V ±12 mA IOZ High-impedance state output current VO = 0 V to VCC ±20 µA IOVCC = 1.8V 200 Input pull-down integrated resistor on all Rpdn k Ω inputs (Dx, CLKSEL, SHTDN, CLKIN) IOVCC = 3.3V 100 disabled, all inputs at GND; 2 100 µA SHTDN = VIL SHTDN = VIH, RL = 100Ω (5 places), grayscale pattern (Figure 5) VCC = 3.3V, fCLK = 75MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 51.9 61 I(IOVCC) with IOVCC = 3.3V 0.4 1.2 mA I(IOVCC) with IOVCC = 1.8V 0.1 SHTDN = VIH, RL = 100Ω (5 places), 50% transition density pattern (Figure 5), VCC = 3.3V, fCLK = 75MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 53.3 64.6 I(IOVCC) with IOVCC = 3.3V 0.6 2.5 mA I(IOVCC) with IOVCC = 1.8V 0.2 SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 6), VCC = 3.6V, fCLK = 75MHz IQ Quiescent current (average) I(VCC) + I(PLLVCC) + I(LVDSVCC) 63.7 76 I(IOVCC) with IOVCC = 3.3V 1.3 3.3 mA I(IOVCC) with IOVCC = 1.8V 0.5 SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 6), fCLK = 100MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 81.6 93 I(IOVCC) with IOVCC = 3.6V 1.6 3.8 mA I(IOVCC) with IOVCC = 1.8V 0.6 SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 6), fCLK = 135MHz I(VCC) + I(PLLVCC) + I(LVDSVCC) 102.2 115 I(IOVCC) with IOVCC = 3.6V 2.1 4.5 mA I(IOVCC) with IOVCC = 1.8V 0.8 CI Input capacitance 2 pF (1) All typical values are at VCC = 3.3 V, TA = 25°C. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): SN75LVDS83B |
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