SWITCHING CHARACTERISTICS

SN65LVCP408

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

MULTIPLEXER

Multiplexer switch time

Multiplexer to valid output

15

ns

DIFFERENTIAL OUTPUTS

Low-to-high propagation

0.5

0.7

ns

delay

Propagation delay input to output, See Figure 6

High-to-low propagation

0.5

0.7

ns

delay

Rise time

90

ps

See Figure 5 and Figure 8

Fall time

90

ps

(2)

20

ps

All outputs terminated with 100

Ω

25

75

ps

150

ps

3-State switch time to

Assumes 50

Ω to Vcm and 150 pF load on each output;

30

ns

Disable

Tested using I2C

3-State switch time to

Assumes 50

Ω to Vcm and 150 pF load on each output;

20

ns

Enable

Tested using I2C

RJ

Device random jitter, rms

0.8

2 ps-rms

Alternating 10-pattern.

0 dB preemphasis

Intrinsic deterministic device

See Figure 8 for the test

4.25 Gbps

30

ps

pattern

circuit.

1.25Gbps;

EQ=13dB

15

Over 25-inch

DJ

FR4 trace

0 dB preemphasis

Absolute deterministic

See Figure 8 for the test

ps

4.25 Gbps;

pattern

circuit.

EQ=13dB

Over FR4 trace

40

2-inch to 43

inches long

(1)

All typical values are at 25°C and with 3.3 V supply unless otherwise noted.

(2)

(3)

(4)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(5)

The SN65LVCP408 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the

LVCP408 typically reduces jitter by 29 ps from the device input to the device output.

(6)

Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP408 output. The value is a real measured

value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated

Copyright © 2009, Texas Instruments Incorporated

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