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ADS62P48IRGCT Datasheet(PDF) 5 Page - Texas Instruments |
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ADS62P48IRGCT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 76 page RECOMMENDED OPERATING CONDITIONS ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 www.ti.com............................................................................................................................................................. SLAS635A – APRIL 2009 – REVISED JUNE 2009 MIN TYP MAX UNIT SUPPLIES AVDD Analog supply voltage 3.15 3.3 3.6 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage range 2 VPP Input common-mode voltage 1.5 ±0.1 V Voltage applied on CM in external reference mode 1.5±0.05 V Maximum analog input frequency with 2 Vpp input amplitude (1) 500 MHz Maximum analog input frequency with 1 Vpp input amplitude (1) 800 MHz CLOCK INPUT Input clock sample rate Enable low speed mode(2) 1 100 ADS62P49 / ADS62P29 MSPS Low speed mode disabled (default mode after reset) >100 250(3) Enable low speed mode 1 100 ADS62P48 / ADS62P28 MSPS Low speed mode disabled (default mode after reset) >100 210 With multiplexed mode enabled(4) 1 65 MSPS Input clock amplitude differential (VCLKP–VCLKM) Sine wave, ac-coupled 0.2 3 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 3.3 V Input clock duty cycle 40% 50% 60% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND 5 pF RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω TA Operating free-air temperature –40 85 °C (1) See the Theory of Operation section for information. (2) Use register bit <ENABLE LOW SPEED MODE>, refer to the Serial Register Map section for information. (3) With LVDS interface only; maximum recommended sample rate with CMOS interface is 210 MSPS. (4) See the Multiplexed Output Mode section for information. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 |
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