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TPS3837K33DBVT Datasheet(PDF) 7 Page - Texas Instruments |
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TPS3837K33DBVT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 11 page  TPS3836E18 / J25 / H30 / L30 / K33 TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33 NANOPOWER SUPERVISORY CIRCUITS SLVS292A – JUNE 2000 – REVISED JANUARY 2002 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25_C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT at VDD VIH = VIT + 0.2 V, VIL = VIT – 0.2 V 6 µs tw Pulse width at MR VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 1 µs switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25_C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t Delay time VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = GND, See timing diagram 5 10 15 ms td Delay time VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = VDD , See timing diagram 100 200 300 ms tPHL Propagation (delay) time, high-to-low-level output VDD to RESET delay (TPS3836 TPS3838) VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 10 µs tPHL Pro agation (delay) time, high to low level out ut (TPS3836, TPS3838) VIL = 1.6 V 50 µs tPLH Propagation (delay) time, low-to-high-level output VDD to RESET delay (TPS3837) VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 10 µs tPLH Pro agation (delay) time, low to high level out ut (TPS3837) VIL = 1.6 V 50 µs tPHL Propagation (delay) time, high-to-low-level output MR to RESET delay (TPS3836, TPS3838) VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, 0.1 µs tPLH Propagation (delay) time, low-to-high-level output MR to RESET delay (TPS3837) VIL = 0.3 × VDD, VIL = 0.7 × VDD 0.1 µs TYPICAL CHARACTERISTICS Table of Graphs FIGURE IDD Supply current vs Supply voltage 1 IMR Manual reset current vs Manual reset voltage 2 VOL Low-level output voltage vs Low-level output current 3 VOH High-level output voltage vs High-level output current 4 Normalized reset threshold voltage vs Free-air temperature 5 Minimum pulse duration at VDD vs VDD Threshold overdrive 6 |
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