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TPS70158PWP Datasheet(PDF) 3 Page - Texas Instruments |
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TPS70158PWP Datasheet(HTML) 3 Page - Texas Instruments |
3 / 34 page TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed block diagram – fixed voltage version UVLO Thermal Shutdown Shutdown V_UVLO + – Current Sense Reference VREF VREF ENA_1 ENA_1 10 k Ω Rising Edge Deglitch 0.95 × VREP FB2 Falling Edge Delay VIN1 PG1 Comp 0.95 × VREF FB1 Rising Edge Deglitch Falling Edge Deglitch 0.83 × VREF FB2 UV Comp Falling Edge Deglitch 0.83 × VREF FB1 UV Comp Power Sequence Logic SHUTDOWN ENA_! ENA_2 VCC Current Sense + – 10 k Ω ENA_2 ENA_2 FB2 VREF VIN1 (2 Pins) GND EN SEQ (see Note B) VIN2 (2 Pins) VOUT1 (2 Pin) VSENSE1 (see Note A) PG1 MR2 RESET MR1 VSENSE2 (see Note A) VOUT2(2 Pin) FB1 VCC NOTES: A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in Application information section. B. If the SEQ terminal is floating at the input, the VOUT2 will power-up first. |
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