TPS70145, TPS70148, TPS70151, TPS70158, TPS70102

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303

RESET timing diagram

NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

VIN1 and VIN2

Vres

(see Note A)

Vres

t

t

t

VOUT2

Threshold

Voltage

RESET

Output

120 ms

Delay

120 ms

Delay

Output

Undefined

Output

Undefined

VIT +(see Note B)

VIT –

(see Note B)

VIT +(see Note B)

B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.

VIT –

(see Note B)

PG timing diagram

NOTES: A. Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC

standards for semiconductor symbology.

Vres

t

t

t

Threshold

Voltage

PG

Output

Output

Undefined

Output

Undefined

VIT+ (see Note B)

VIT +(see Note B)

B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis

VIN1 and VIN2

VOUT2

Vres

(see Note A)

VIT –

(see Note B)

VIT –

(see Note B)