TPS70745, TPS70748, TPS70751, TPS70758, TPS70702

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS291 – MAY 2000

5

POST OFFICE BOX 655303

NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

VIN2

VRES

(see Note A)

VRES

t

t

t

VOUT2

Threshold

Voltage

RESET

Output

120 ms

Delay

120 ms

Delay

Output

Undefined

Output

Undefined

VIT +(see Note B)

VIT –

(see Note B)

VIT +(see Note B)

B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.

VIT –

(see Note B)

PG1 timing diagram

NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC

standards for semiconductor symbology.

VPG1

t

t

t

Threshold

Voltage

PG1

Output

Output

Undefined

Output

Undefined

VIT+ (see Note B)

VIT +(see Note B)

B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.

VIN1

VOUT2

VPG1

(see Note A)

VIT –

(see Note B)

VIT –

(see Note B)

VUVLO

VUVLO

30

µs