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PO74HSTL314ASR Datasheet(PDF) 5 Page - Potato Semiconductor Corporation |
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PO74HSTL314ASR Datasheet(HTML) 5 Page - Potato Semiconductor Corporation |
5 / 7 page Test Waveforms 07/10/06 3.3V 2:4 Differential Clock/Data Fanout Buffer Copyright © Potato Semiconductor Corporation 5 PO74HSTL314A 500MHz HSTL Potato Chip VPP RANGE 0V-VCC FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS FIGURE 2. HSTL/HSTL OUTPUT FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for both CLKA or CLKB to output pair VPP TPHL TPLH TPD INPUT CLOCK OUTPUT CLOCK ANOTHER OUTPUT CLOCK VO tSK(O) VCC= 3.3V VEE=0.0V VIH VIL VPP VCC VEE VO tr,tf, 20-80% |
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