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PO74G139ASU Datasheet(PDF) 1 Page - Potato Semiconductor Corporation |
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PO74G139ASU Datasheet(HTML) 1 Page - Potato Semiconductor Corporation |
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1 / 6 page  Copyright © Potato Semiconductor Corporation 74 Series GHz Logic PO74G139A DUAL2-LINETO4-LINEDECODER/DEMULTIPLEXER 02/07/07 1 FEATURES: . Patented technology . Operating frequency up to 1.125GHz with 2pf load . Operating frequency up to 800MHz with 5pf load . Operating frequency up to 350MHz with 15pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 1.7ns max with 15pf load . Low input capacitance: 4pf typical . Available in 16 pin SOIC package Pin Configuration Logic Block Diagram Pin Description DESCRIPTION: Potato Semiconductor’s PO74G139A is designed for world top performance using submicron CMOS technology to achieve 1.125GHz TTL /CMOS output frequency with less than 1.7ns propagation delay. This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. The PO74G139A comprises two individual 2-line to 4-line decoders in a single package. Theactive- lowenable (G) input can be used as a data line in demultiplexing applications. This decoder/ demulti- plexer features fully buffered inputs, each of which represents only one normalized- load to itsdriving circuit. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 Select Inputs Select Inputs 2B 2A 2G 1B 1A 1G Data Outputs 2Y3 2Y2 2Y1 2Y0 1Y3 1Y2 1Y1 1Y0 1 2 3 15 14 13 4 5 6 7 12 11 10 9 INPUTS OUTPUTS SELECT G B A Y3 Y2 Y1 Y0 L L L H H H L L L H H H L H L H L H L H H L H H L H H H H X X H H H H |
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