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PCS5P9773G-52-ER Datasheet(PDF) 7 Page - PulseCore Semiconductor

Part # PCS5P9773G-52-ER
Description  2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
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Manufacturer  PULSECORE [PulseCore Semiconductor]
Direct Link  http://www.onsemi.com/
Logo PULSECORE - PulseCore Semiconductor

PCS5P9773G-52-ER Datasheet(HTML) 7 Page - PulseCore Semiconductor

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September 2006
PCS5I9773
rev 0. 4
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
7 of 16
Notice: The information in this document is subject to change without notice.
AC Electrical Specifications (VDD = 2.5V ±5%, T
A = -40°C to +85°C)
7
Parameter
Description
Condition
Min
Typ
Max
Unit
fVCO
VCO Frequency
200
380
MHz
÷4 Feedback
50
95
÷6 Feedback
33.3
63.3
÷8 Feedback
25
47.5
÷10 Feedback
20
38
÷12 Feedback
16.6
31.6
÷16 Feedback
12.5
23.75
÷20 Feedback
10
19
÷24 Feedback
8.3
15.8
÷32 Feedback
6.25
11.8
÷40 Feedback
5
9.5
fin
Input Frequency
Bypass mode (PLL_EN = 0)
0
200
MHz
frefDC
Input Duty Cycle
25
75
%
VPP
Peak-Peak Input Voltage
LVPECL
500
1000
mV
VCMR
Common Mode Range
8
LVPECL
1.2
VDD– 0.6
V
tr, tf
TCLK Input Rise/FallTime
0.7V to 1.7V
1.0
nS
÷2 Output
100
190
÷4 Output
50
95
÷6 Output
33.3
63.3
÷8 Output
25
47.5
÷10 Output
20
38
÷12 Output
16.6
31.6
÷16 Output
12.5
23.75
÷20 Output
10
19
fMAX
Maximum Output Frequency
÷24 Output
8.3
15.8
MHz
fSCLK
Serial Clock Frequency
20
MHz
fMAX < 100MHz
47.5
52.5
DC
Output Duty Cycle
fMAX > 100MHz
45
55
%
tr, tf
Output Rise/Fall times
0.6V to 1.8V
0.1
1.0
nS
TCLK to FB_IN
-125
125
t(φ)
Propagation Delay
(static phase offset)
PCLK to FB_IN
-125
125
pS
Notes:
7. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing
lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).


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