September 2006

PCS2P20805A

rev 0.3

2.5V CMOS Dual 1-To-5 Clock Driver

7 of 11

Notice: The information in this document is subject to change without notice.

Test Circuits and Waveforms

INPUT

OUTPUT

0V

1.25V

2.5V

1.7V

1.25V

0.7V

Propagation Delay

2.5V

INPUT

0V

1.25V

1.25V

OUTPUT

Pulse Skew

INPUT

0V

1.25V

2.5V

1.25V

Package 1

OUTPUT

1.25V

Package 2

OUTPUT

Part-to- Part Skew

Note: Part-to- Part Skew is for package and speed grade.

ENABLE

2.5V

1.25V

0V

DISABLE

0.3V

0.3V

1.25V

1.25V

SWITCH

CLOSED

SWITCH

OPEN

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

Enable and Disable Times

Note: 1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH