September 2006

PCS2I2310ANZ

rev 0.5

3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs

6 of 12

Notice: The information in this document is subject to change without notice.

SDRAM Enable and Disable Times

Test Circuit for IIC Rise and Fall Times

Figure 3. Test Circuit for IIC

GND

DUT

OE INPUT

Figure 2. 3-State Enable and Disable times

OUTPUT

LOW-to-OFF

OFF-to-LOW

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

Outputs

disabled

Outputs

enabled

Outputs

enabled

GND