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 PULSECORE
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January 2007 ASM3P2869A rev 1.7 Notice: The information in this document is subject to change without notice. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Low Power Peak EMI Reducing Solution Features • Generates an EMI optimized clock signal at the output • Integrated loop filter components • Operates with a 3.3V /2.5V supply • Operating current less than 4mA • Low power CMOS design • Input frequency range: 6MHz to 12MHz for 2.5V : 6MHz to 13MHz for 3.3V • Generates a 1X low EMI spread spectrum clock of the input frequency • Frequency deviation: ±1%(Typ) @ 10MHz • Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin TSSOP packages Product Description The ASM3P2869A is a versatile spread spectrum frequency modulator designed specifically for a wide range of clock frequencies. The ASM3P2869A reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of all clock dependent signals. The ASM3P2869A allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding that are traditionally required to pass EMI regulations. The ASM3P2869A uses the most efficient and optimized modulation profile approved by the FCC and is implemented by using a proprietary all digital method. The ASM3P2869A modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. Applications The ASM3P2869A is targeted towards all portable devices with very low power requirements like MP3 players, Notebooks and digital still cameras. Key Specifications Description Specification Supply voltages VDD = 2.5V / 3.3V Cycle-to-Cycle Jitter 200pS ( Max) Output Duty Cycle 45/55% Modulation Rate Equation FIN/256 Frequency Deviation ±1% (Typ) @ 10MHz Block Diagram REFOUT VSS ModOUT XOUT XIN Frequency Divider Feedback Divider Modulation Phase Detector Loop Filter VCO Output Divider PLL VDD Crystal Oscillator |
