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| ASM3P622S01B |
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 PULSECORE
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5 page 
May 2007 ASM3P622S01B/J rev 0.4 Low Frequency Timing-Safe™ Peak EMI Reduction IC 5 of 12 Notice: The information in this document is subject to change without notice. Switching Characteristics for ASM3P622S01B/J Parameter Description Test Conditions Min Typ Max Unit 1/t1 Output Frequency 30pF load 4 20 MHz Duty Cycle 2 = (t2 / t1) * 100 Measured at VDD/2 40 50 60 % t3 Output Rise Time 1, 2 Measured between 0.8V and 2.0V 2.5 nS t4 Output Fall Time 1, 2 Measured between 2.0V and 0.8V 2.5 nS t5 Output-to-output skew 2 All outputs equally loaded 250 pS t6 Delay, CLKIN Rising Edge to CLKOUT Rising Edge 2 Measured at VDD /2 ±250 pS t7 Device-to-Device Skew 2 Measured at VDD/2 on the CLKOUT pins of the device 700 pS tJ Cycle-to-cycle jitter 2 Loaded outputs 200 pS tLOCK PLL Lock Time 2 Stable power supply, valid clock presented on CLKIN pin 1.0 mS Note: 1. The parameters specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production |
