ASM2I5T905AG-28TR datasheet(11/19 Pages) PULSECORE

Part #	ASM2I5T905AG-28TR

Description	2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

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Manufacturer	PULSECORE [PulseCore Semiconductor]

Direct Link	http://www.onsemi.com/

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11 / 19 page

November 2006

ASM2P5T905A

rev 0.2

2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

11 of 19

Notice: The information in this document is subject to change without notice.

DC Electrical Characteristics over Operating Range for 1.8V LVTTL

1

Symbol

Parameter

Test Conditions

Min.

Typ

8

Max

Unit

Input Characteristics

IIH

Input HIGH Current

12

VDD = 2.6V

VI = VDDQ/GND

±5

IIL

Input LOW Current

12

VDD = 2.6V

VI = GND/VDDQ

±5

µA

VIK

Clamp Diode Voltage

VDD = 2.4V, IIN= -18mA

-0.7

- 1.2

V

VIN

DC Input Voltage

- 0.3

VDDQ+ 0.3

V

Single-Ended Inputs

2

VIH

DC Input HIGH

1.073

10

V

VIL

DC Input LOW

0.683

11

V

Differential Inputs

VDIF

DC Differential Voltage

3,9

0.2

V

VCM

DC Common Mode Input

Voltage

4,9

825

900

975

mV

VIH

DC Input HIGH

5,6,9

VREF+ 100

mV

VIL

DC Input LOW

5,7,9

VREF- 100

mV

VREF

Single-Ended Reference

Voltage

5,9

900

mV

Output Characteristics

VOH

Output HIGH Voltage

IOH= -6mA

VDDQ- 0.4

V

IOH= -100µA

VDDQ- 0.1

V

VOL

Output LOW Voltage

IOL= 6mA

0.4

V

IOL= 100µA

0.1

V

NOTES:

1. See RECOMMENDED OPERATING RANGE table.

2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.

3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input

level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential

voltage must be achieved to guarantee switching to a new state.

4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.

5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is

constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage

range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances.

6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.

7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.

8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.

9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface

table should be referenced.

10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD

is 1.8V ±0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator

was designed to accept the calculated worst case value (VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.

11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD

is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator

was designed to accept the calculated worst case value (VIH = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.

12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.

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