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ASM2I99456G-32-ER Datasheet(PDF) 7 Page - PulseCore Semiconductor |
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ASM2I99456G-32-ER Datasheet(HTML) 7 Page - PulseCore Semiconductor |
7 / 14 page November 2006 ASM2I99456 rev 0.3 3.3V/2.5V LVCMOS Clock Fanout Buffer 7 of 14 Notice: The information in this document is subject to change without notice. Applications Information Driving Transmission Lines The ASM2I99456 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to VCC÷2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the ASM2I99456 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the ASM2I99456 clock driver is effectively doubled due to its capability to drive multiple lines. Figure 1. Single versus Dual Transmission Lines The waveform plots in Figure 2. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the ASM2I99456 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the ASM2I99456. The output waveform in Figure 2. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 ÷ (RS+R0 +Z0)) Z0 = 50Ω || 50Ω RS = 36Ω || 36Ω R0 = 14Ω VL = 3.0 ( 25 ÷ (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). Figure 2. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. 14 Ω + 22Ω || 22Ω = 50Ω || 50Ω 25 Ω = 25Ω ASM2I99456 OUTPUT BUFFER 14Ω Z0=50Ω RS=22Ω Z0=50Ω RS=22Ω ASM2I99456 OUTPUT BUFFER 14Ω Z0=50Ω RS=36Ω ASM2I99456 OUTPUT BUFFER 14Ω Z0=50Ω RS=36Ω Z0=50Ω RS=36Ω 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 TIME (nS) In OutA tD = 3.8956 OutB tD = 3.9386 |
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