ASM2P5T905AF-28TR datasheet(7/19 Pages) PULSECORE

Part #	ASM2P5T905AF-28TR

Description	2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

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Manufacturer	PULSECORE [PulseCore Semiconductor]

Direct Link	http://www.onsemi.com/

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7 / 19 page

November 2006

ASM2P5T905A

rev 0.2

2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

7 of 19

Notice: The information in this document is subject to change without notice.

DC Electrical Characteristics over Operating Range for eHSTL

1

Symbol

Parameter

Test Conditions

Min

Typ

7

Max

Unit

Input Characteristics

IIH

Input HIGH Current

9

VDD = 2.6V

VI = VDDQ/GND

±5

IIL

Input LOW Current

9

VDD = 2.6V

VI = GND/VDDQ

±5

µA

VIK

Clamp Diode Voltage

VDD = 2.4V, IIN = -18mA

- 0.7

- 1.2

V

VIN

DC Input Voltage

-0.3

+3.6

V

VDIF

DC Differential Voltage

2,8

0.2

V

VCM

DC Common Mode Input

Voltage

3,8

800

900

1000

mV

VIH

DC Input HIGH

4,5,8

VREF+ 100

-

mV

VIL

DC Input LOW

4,6,8

VREF-100

mV

VREF

Single-Ended Reference

Voltage

4,8

900

mV

Output Characteristics

IOH= -8mA

VDDQ- 0.4

V

VOH

Output HIGH Voltage

IOH= -100µA

VDDQ- 0.1

V

IOL= 8mA

0.4

V

VOL

Output LOW Voltage

IOL= 100µA

0.1

V

NOTES:

1. See RECOMMENDED OPERATING RANGE table.

2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input

level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential

voltage must be achieved to guarantee switching to a new state.

3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.

4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF.

5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.

6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.

7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.

8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface

table should be referenced.

9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.

Power Supply Characteristics for eHSTL Outputs

1

Symbol

Parameter

Test Conditions

2

Typ

Max

Unit

IDDQ

Quiescent VDD Power Supply

Current

VDDQ= Max., Reference Clock = LOW

3

Outputs enabled, All outputs unloaded

20

30

mA

IDDQQ

Quiescent VDDQ Power Supply

Current

VDDQ= Max., Reference Clock = LOW

3

Outputs enabled, All outputs unloaded

0.1

0.3

mA

IDDD

Dynamic VDD Power Supply

Current per Output

VDD= Max., VDDQ= Max., CL= 0pF

10

20

µA/MHz

IDDDQ

Dynamic VDDQ Power Supply

Current per Output

VDD= Max., VDDQ= Max., CL= 0pF

20

30

µA/MHz

VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz,

CL= 15pF

20

30

ITOT

Total Power VDD Supply

Current

VDDQ= 1.8V, FREFERENCE CLOCK= 250MHz,

CL= 15pF

25

40

mA

VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz,

CL= 15pF

20

40

ITOTQ

Total Power VDDQ Supply

Current

VDDQ= 1.8V, FREFERENCE CLOCK= 250MHz,

CL= 15pF

40

80

mA

NOTES:

1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.

2. The termination resistors are excluded from these measurements.

3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.

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