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April 2007 ASM2I9940L rev 1.2 Low Voltage 1:18 Clock Distribution Chip 4 of 13 Notice: The information in this document is subject to change without notice. Table 5. DC Characteristics (T A =-40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%) Symbol Characteristic Min Typ Max Unit Condition VIH Input HIGH Voltage CMOS_CLK 2.0 VCCI V VIL Input LOW Voltage CMOS_CLK 0.8 V VPP Peak–to–Peak Input Voltage PECL_CLK 500 1000 mV VCMR Common Mode Range PECL_CLK VCC-1.4 VCC-0.6 V VOH Output HIGH Voltage 2.4 V IOH = –20mA VOL Output LOW Voltage 0.5 V IOH = 20mA IIN Input Current ±200 µA CIN Input Capacitance 4.0 pF Cpd Power Dissipation Capacitance 10 pF per output ZOUT Output Impedance 18 23 28 Ω ICC Maximum Quiescent Supply Current 0.5 1.0 mA Table 6. AC Characteristics (T A = -40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%) Symbol Characteristic Min Typ Max Unit Condition Fmax Maximum Input Frequency 250 MHz tPLH Propagation Delay PECL_CLK < 150MHz CMOS_CLK < 150MHz 2.0 1.7 2.7 2.5 3.4 3.0 nS Note 1. tPLH Propagation Delay PECL_CLK > 150MHz CMOS_CLK > 150MHz 2.0 1.8 2.9 2.5 3.7 3.2 nS tsk(o) Output-to-output Skew PECL_CLK CMOS_CLK 150 150 pS Note 1. tsk(pp) Part-to-Part Skew PECL_CLK < 150MHz CMOS_CLK < 150MHz 1.5 1.3 nS Notes 1,2 tsk(pp) Part-to-Part Skew PECL_CLK > 150MHz CMOS_CLK > 150MHz 1.8 1.5 nS Notes 1,2 tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK 850 750 pS Notes 1,3 DC Output Duty Cycle fCLK < 134 MHz fCLK <250 MHz 45 40 50 50 55 60 % % Input DC = 50% Input DC = 50% tr, tf Output Rise/Fall Time 0.3 1.1 nS 0.5 – 2.4 V Note: 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew. |
