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TMS44400PDGA Datasheet(PDF) 9 Page - Texas Instruments |
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TMS44400PDGA Datasheet(HTML) 9 Page - Texas Instruments |
9 / 25 page TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMHS562C – MAY 1995 – REVISED NOVEMBER 1996 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’4x400 - 60 ’4x400P - 60 ’4x400 - 70 ’4x400P - 70 ’4x6400 - 80 ’4x400P - 80 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write (see Note 8) 110 130 150 ns tRWC Cycle time, read-write 155 181 205 ns tPC Cycle time, page-mode read or write (see Note 9) 40 45 50 ns tPRWC Cycle time, page-mode read-write 85 96 105 ns tRASP Pulse duration, RAS low, page mode (see Note 10) 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, RAS low, nonpage mode (see Note 10) 60 10 000 70 10 000 80 10 000 ns tRASS Pulse duration, RAS low, self refresh 100 100 100 µs tCAS Pulse duration, CAS low (see Note 11) 10 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tRPS Precharge time after self refresh using RAS 110 130 150 ns tWP Pulse duration, write 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data (see Note 12) 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low (early-write operation only) 0 0 0 ns tWSR Setup time, W high (CBR refresh only) 10 10 10 ns tWTS Setup time, W low (test mode only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tDHR Hold time, data after RAS low (see Note 13) 50 55 60 ns tDH Hold time, data (see Note 12) 10 15 15 ns tAR Hold time, column address after RAS low (see Note 13) 50 55 60 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 14) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 14) 0 0 0 ns tWCH Hold time, W low after CAS low (early-write operation only) 10 15 15 ns tWCR Hold time, W low after RAS low (see Note 13) 50 55 60 ns tWHR Hold time, W high (CBR refresh only) 10 10 10 ns tWTH Hold time, W low (test mode only) 10 10 10 ns tCHS Hold time, CAS low after RAS high (self refresh) – 50 – 50 – 50 ns tOEH Hold time, OE command 15 18 20 ns tOED Hold time, OE to data delay 15 18 20 ns NOTES: 8. All cycle times assume tT = 5 ns. 9. To ensure tPC min, tASC should be ≥ tCP . 10. In a read-write cycle, tRWD and tRWL must be observed. 11. In a read-write cycle, tCWD and tCWL must be observed. 12. Referenced to the later of CAS or W in write operations 13. The minimum value is measured when tRCD is set to tRCD min as a reference. 14. Either tRRH or tRCH must be satisfied for a read cycle. |
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