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TMS320C6202BGNZ300 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6202BGNZ300 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 86 page TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS104A – OCTOBER 1999 – REVISED MARCH 2000 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table of Contents input and output clocks 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 38 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 41 . . . . . . . . . . . . . . . . . synchronous DRAM timing 43 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 50 . . . . . . . . . . . . . . . . . . . . . . . . . . expansion bus synchronous FIFO timing 51 . . . . . . . . . . . . expansion bus asynchronous peripheral timing 53 . . . . . . expansion bus synchronous host port timing 56 . . . . . . . . expansion bus asynchronous host port timing 62 . . . . . . . XHOLD/XHOLDA timing 64 . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 66 . . . . . . . . . . . . . DMAC, timer, power-down timing 78 . . . . . . . . . . . . . . . . . . JTAG test-port timing 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GJL/GLS/GLW BGA packages (bottom view) 3 . . . . . . . . . . device selection guide 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ’C62x device compatibility 6 . . . . . . . . . . . . . . . . . . . . . . . . . . functional and CPU block diagram (’C62x devices) 7 . . . . . CPU description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal groups description 10 . . . . . . . . . . . . . . . . . . . . . . . . . . signal descriptions 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 31 . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 32 . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 33 parameter measurement information 34 . . . . . . . . . . . . . . . . |
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