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TMS320C50 Datasheet(PDF) 52 Page - Texas Instruments |
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TMS320C50 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 91 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 internal divide-by-two clock option with external crystal The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1 is one-half of the crystal’s oscillating frequency. The crystal should be in either fundamental or overtone operation and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned-LC circuit. Figure 12 shows an external crystal (fundamental frequency) connected to the on-chip oscillator. recommended operating conditions for internal divide-by-two clock option MIN NOM MAX UNIT TMS320C5x-40 0† 40.96 TMS320C5x-57 0† 57.14 MHz TMS320C5x-80 0† 80 MHz fclk Input clock frequency TMS320C5x-100‡ 0† 100 TMS320LC5x-40 0† 40 TMS320LC5x-50 0† 50 MHz TMS320LC5x-80 0† 80 C1, C2 Load capacitance 10 pF † This device utilizes a fully static design and, therefore, can operate with input clock cycle time (tc(CI)) approaching ∞. The device is characterized at frequencies approaching 0 Hz, but is tested at fclk = 6.7 MHz to meet device test time requirements. ‡ ’320C51, ’320C52 currently available at this clock speed X1 X2 / CLKIN C1 C2 Crystal Figure 12. Internal Clock Option |
Similar Part No. - TMS320C50 |
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Similar Description - TMS320C50 |
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