TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS189 – MARCH 1999

1

POST OFFICE BOX 655303

Consumption

1

µs in Fast Mode

3.5

µs in Slow Mode

Reference Voltage

applications

description

The TLV5639 is a 12-bit voltage output digital-to-analog converter (DAC) with a microprocessor compatible

parallel interface. It is programmed with a 16-bit data word containing 4 control and 12 data bits. Developed for

a wide range of supply voltages, the TLV5639 can be operated from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows

the designer to optimize speed versus power dissipation. Because of its ability to source up to 1 mA, the internal

reference can also be used as a system reference. With its on-chip programmable precision voltage reference,

the TLV5639 simplifies overall system design. The settling time and the reference voltage can be chosen by

the control bits within the 16-bit data word.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It

is available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

TA

SOIC

(DW)

TSSOP

(PW)

0

°C to 70°C

TLV5639CDW

TLV5639CPW

–40

°C to 85°C

TLV5639IDW

TLV5639IPW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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10

20

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12

11

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D1

D0

CS

WE

LDAC

REG

AGND

OUT

REF

DW OR PW PACKAGE

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