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TLV5625IDRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV5625IDRG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 15 page TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued) digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD 1 µA IIL Low-level digital input current VI = 0 V –1 µA Ci Input capacitance 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t (FS) Output settling time full scale RL = 10 kΩ,CL = 100 pF, Fast 2.5 µs ts(FS) Output settling time, full scale L , L , See Note 11 Slow 12 µs t (CC) Output settling time code to code RL = 10 kΩ,CL = 100 pF, Fast 1 µs ts(CC) Output settling time, code to code L , L , See Note 12 Slow 2 µs SR Slew rate RL = 10 kΩ,CL = 100 pF, Fast 3 V/ µs SR Slew rate L , L , See Note 13 Slow 0.5 V/ µs Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD 5 nV–s SNR Signal-to-noise ratio 52 54 SINAD Signal-to-noise + distortion fs = 102 kSPS, fout = 1 kHz, 48 49 dB THD Total harmonic distortion s , out , RL = 10 kΩ,CL = 100 pF –50 –48 dB SFDR Spurious free dynamic range 48 50 NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage. |
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