Electronic Components Datasheet Search |
|
TLV5625CDRG4 Datasheet(PDF) 10 Page - Texas Instruments |
|
|
TLV5625CDRG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 15 page TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS233A – JULY 1999 – REVISED MARCH 2000 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION general function The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by the reference) is given by: 2REF CODE 0x1000 [V] Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0. A power-on reset initially puts the internal latches to a defined state (all bits zero). serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 2 shows examples of how to connect the TLV5625 to TMS320, SPI ™, and Microwire™. TMS320 DSP FSX CLKX DX TLV5625 SCLK DIN CS SPI I/O SCK MOSI TLV5625 SCLK DIN CS Microwire I/O SK SO TLV5625 SCLK DIN CS Figure 12. Three-Wire Interface Notes on SPI ™ and Microwire™: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI ™ and Microwire™) two write operations must be performed to program the TLV5625. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax + 1 t whmin ) twlmin + 20 MHz The maximum update rate is: f updatemax + 1 16 t whmin ) twlmin + 1.25 MHz Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5625 should also be considered. |
Similar Part No. - TLV5625CDRG4 |
|
Similar Description - TLV5625CDRG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |