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TLV5626CD Datasheet(PDF) 11 Page - Texas Instruments |
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TLV5626CD Datasheet(HTML) 11 Page - Texas Instruments |
11 / 16 page TLV5626 2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS236 –JUNE 1999 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION Notes on SPI ™ and Microwire™: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPI ™ and Microwire™), two write operations must be performed to program the TLV5626. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax + 1 t whmin ) twlmin + 20 MHz The maximum update rate is: f updatemax + 1 16 t whmin ) twlmin + 1.25 MHz The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5626 has to be considered, too. data format The 16-bit data word for the TLV5626 consists of two parts: D Program bits (D15..D12) D New data (D11..D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1 SPD PWR R0 12 Data bits SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC Value 0 0 0 0 If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: |
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