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TLV5590ED Datasheet(PDF) 10 Page - Texas Instruments |
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TLV5590ED Datasheet(HTML) 10 Page - Texas Instruments |
10 / 16 page TLV5590 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEX t PAGER CHIPSET SLAS134B – NOVEMBER 1995 – REVISED NOVEMBER 1996 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION The thresholds for the ADC comparators are set by capacitor ratios in switched-capacitor comparators. For a 2-bit ADC, three comparators are used with thresholds set as shown in Table 3. Table 3. Comparators and Associated Threshold Values (see Notes 4 and 5) COMPARATOR VALUE UNIT Lower threshold ((peak – valley) x 50/256) + valley V Middle threshold ((peak – valley) x 134/256) + valley V Upper threshold ((peak – valley) x 217/256) + valley V NOTES: 4. The constants 50/256, 134/256, and 217/256 have a ± 5% tolerance. 5. The comparator thresholds are measured with the input voltage level of the SIG terminal at 125 mV ac centered on 800 mV dc and the input voltage at the DC OFFSET terminal is 800 mV dc. peak and valley timing The peak and valley attack and delay times are controlled by two 8-bit up/down counters clocked by the CLK input. The rate that the counters are clocked depends on whether the counters are in attack or decay mode. The peak counter is in attack mode when the input signal amplitude is greater than the output voltage from the peak DAC, and it is in decay mode when the input signal amplitude is less that the peak DAC output voltage. The valley counter is in attack mode when the input signal amplitude is less than the output voltage from the valley DAC, and it is in decay mode when the input signal amplitude is greater than the valley DAC output voltage. When TRACKINH is held high, the attack and decay enable inputs to the peak and valley counters are disabled. When held low the attack and decay enable inputs to the peak and valley counters are enabled. The effect of the TRACKINH signal is exactly the same as when the device is configured in hold mode. slow-acquisition-mode attack and decay times The attack rate is calculated equal to [VDD × f(CLK) × 2] / 256 / (TRACKINH duty cycle). So the peak and valley counter is incremented/decremented by a count of 2 on every clock cycle when the input signal amplitude is greater or less than the peak and valley DAC output voltage. The decay rate is calculated equal to [VDD × f(CLK)] / (256 × 40) / (TRACKINH duty cycle). So the peak and valley counter is decremented or incremented once every 40 clock cycles when the input signal amplitude is less or greater than the peak and valley DAC output voltage. When the counters receive an attack enable at the same time as a decay enable then the attack enable takes precedence. The decay counter is reset to 1 after an attack and reset to 40 following a decay. With a VDD supply variation of 2.7 V to 3.3 V, and a fixed clock input of 38.4 kHz, the attack and decay times are given in Table 4. Table 4. Slow Acquisition Mode Attack and Decay Times DESCRIPTION CONDITIONS MIN MAX UNIT Attack Rate (ATTR) TRACKINH = Low 810 990 mV/ms Decay Rate (DECR) TRACKINH = Low 10.125 12.375 mV/ms |
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