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TLV2548IPW Datasheet(PDF) 7 Page - Texas Instruments |
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TLV2548IPW Datasheet(HTML) 7 Page - Texas Instruments |
7 / 39 page TLV2544, TLV2548 2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 control and timing (continued) configuration Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once configured after first power up, the information is retained in the H/W or S/W power down state. When the device is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed. The status of the CFR can be read with a read CFR command when the device is programmand for one-shot conversion mode (CFR D[6,5] = 00). Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions BIT DEFINITION D11 Reference select 0: External 1: internal D10 Internal reference voltage select 0: Internal ref = 4 V 1: internal ref = 2 V D9 Sample period select 0: Short sampling 12 SCLKs (1x sampling time) 1: Long sampling 24 SCLKs (2x sampling time) D(8–7) Conversion clock source select 00: Conversion clock = internal OSC 01: Conversion clock = SCLK 10: Conversion clock = SCLK/4 11: Conversion clock = SCLK/2 D(6,5) Conversion mode select 00: Single shot mode 01: Repeat mode 10: Sweep mode 11: Repeat sweep mode D(4,3)† TLV2548 TLV2544 Sweep auto sequence select 00: 0–1–2–3–4–5–6–7 01: 0–2–4–6–0–2–4–6 10: 0–0–2–2–4–4–6–6 11: 0–2–0–2–0–2–0–2 Sweep auto sequence select 00: N/A 01: 0–1–2–3–0–1–2–3 10: 0–0–1–1–2–2–3–3 11: 0–1–0–1–0–1–0–1 D2 EOC/INT – pin function select 0: Pin used as INT 1: Pin used as EOC D(1,0) FIFO trigger level (sweep sequence length) 00: Full (INT generated after FIFO level 7 filled) 01: 3/4 (INT generated after FIFO level 5 filled) 10: 1/2 (INT generated after FIFO level 3 filled) 11: 1/4 (INT generated after FIFO level 1 filled) † These bits only take effect in conversion modes 10 and 11. sampling The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3). |
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