TLV2541, TLV2542, TLV2545

2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245 –MARCH 2000

10

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SINAD

Signal to noise ratio +distortion

200 KSPS, VDD = VREF = 5.5 V

70

72

dB

SINAD

Signal-to-noise ratio +distortion

150 KSPS, VDD = VREF = 2.7 V

68

71

dB

THD

Total harmonic distortion

200 KSPS, VDD = VREF = 5.5 V

–84

–80

dB

THD

Total harmonic distortion

150 KSPS, VDD = VREF = 2.7 V

–84

–80

dB

ENOB

Effective number of bits

200 KSPS, VDD = VREF = 5.5 V

11.8

Bits

ENOB

Effective number of bits

150 KSPS, VDD = VREF = 2.7 V

11.6

Bits

SFDR

Spurious free dynamic range

200 KSPS, VDD = VREF = 5.5 V

–84

–80

dB

SFDR

Spurious free dynamic range

150 KSPS, VDD = VREF = 2.7 V

–84

–80

dB

Analog Input

Full power bandwidth, –3 dB

1

MHz

Full-power bandwidth, –1 dB

500

kHz

external reference specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference input voltage

VDD = =2.7 V ~ 5.5 V

VDD

V

VDD =5 5V

CS = 1,

SCLK = 0

100

M

Ω

Reference input impedance

VDD = 5.5 V

CS = 0,

SCLK = 20 MHz

20

25

k

Ω

Reference input impedance

VDD =2 7V

CS = 1,

SCLK = 0

100

M

Ω

VDD = 2.7 V

CS = 0,

SCLK = 20 MHz

20

25

k

Ω

Reference current

VDD = VREF = 5.5 V,

CS = 0,

SCLK = 20 MHz

100

400

µA

Reference current

VDD = VREF =2.7 V,

CS = 0,

SCLK = 20 MHz

50

200

µA

VDD =VREF =5 5V

CS = 1,

SCLK = 0

5

15

Reference input capacitance

VDD = VREF = 5.5 V

CS = 0,

SCLK = 20 MHz

20

45

50

pF

Reference input capacitance

VDD =VREF =2 7 V

CS = 1,

SCLK = 0

5

15

pF

VDD = VREF =2.7 V

CS = 0,

SCLK = 20 MHz

20

45

50

VREF

Reference voltage

VDD = =2.7 V – 5.5 V

VDD

V

noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

INL

Integral linearity error (see Note 5)

±0.6

±1

LSB

DNL

Differential linearity error

See Note 4

±0.5

±1

LSB

EO

Offset error (see Note 6)

See Note 4

TLV2541/42

±1.5

LSB

EO

Offset error (see Note 6)

See Note 4

TLV2545

±2.5

LSB

EG

Gain error (see Note 6)

See Note 4

TLV2541/42

±2

LSB

EG

Gain error (see Note 6)

See Note 4

TLV2545

±5

LSB

Et

Total unadjusted error (see Note 7)

See Note 4

TLV2541/42

±2

LSB

Et

Total unadjusted error (see Note 7)

See Note 4

TLV2545

±5

LSB

NOTES:

4. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that

applied to REFM convert as all zeros (0000000000).

5. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

7. Total unadjusted error comprises linearity, zero, and full-scale errors.