TLV2544, TLV2548

2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999

11

POST OFFICE BOX 655303

read cycle (read FIFO or read CFR) (continued)

FIFO read cycle

The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read

command. The first FIFO content is output immediately before the command is decoded. If this command is

not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read

command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is

because the read cycle does not generate EOC or INT nor does it carry out any conversion.

SCLK

CS

FS

SDI

INT

EOC

SDO

ID15

ID14

ID13

ID12

ID14

OD8

OD7

OD5

OD0

12

3

4

5

6

713

14

15

16

1

12

OD11 OD10

OD9

ID15

OD6

Figure 4. TLV2544/TLV2548 Continuous FIFO Read Cycle (FS = 1)

(controlled by SCLK, SCLK can stop between each 16 SCLKs)