TLV2543C, TLV2543I

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS096B – MARCH 1995 – REVISED OCTOBER 1995

4

POST OFFICE BOX 655303

converter operation

The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle, and 2) the

actual conversion cycle. The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16

clock periods depending on the selected output data length.

1.

I/O cycle

During the I/O cycle, two operations take place simultaneously.

a.

An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data

is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after

the first eight clocks during 12- or 16-clock I/O transfers.

b.

The data output with a length of 8, 12, or 16 bits is provided serially on DATA OUT. When CS is held low,

the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the

first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion

period, and after the first output data bit each succeeding bit is clocked out on the falling edge of each

succeeding I/O CLOCK.

2.

Conversion cycle

The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to the

I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on

the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when

conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O

cycle is completed, which minimizes the influence of external digital noise on the accuracy of the

conversion.

power up and initialization

After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data

register is set to all zeros. The contents of the output data register are random, and the first conversion result

should be ignored. To initialize during operation, CS is taken high and returned low to begin the next I/O cycle.

The first conversion after the device has returned from the power-down state may not read accurately due to

internal device settling.

operational terminology

Previous (N – 1) conversion cycle

The conversion cycle prior to the current I/O cycle.

Current (N) I/O cycle

The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks

the digital result from the previous conversion cycle from DATA OUT. The last falling edge of the clock in

the I/O CLOCK sequence signifies the end of the current I/O cycle.

Current (N) conversion cycle

Immediately after the current I/O cycle, the current conversion cycle starts. When the current conversion

cycle is complete, the current conversion result is loaded into the output register.

Current (N) conversion result

The result of the current conversion cycle that is serially shifted out during the next I/O cycle.

Next (N + 1) I/O cycle

The I/O cycle after the current conversion cycle.

Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during

the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even

when this corrupts the output data from the previous conversion. The current conversion begins

immediately after the twelfth falling edge of the current I/O cycle.

data input

The data input is internally connected to an 8-bit serial-input address and control register. The register defines

the operation of the converter and the output data length. The host provides the data word with the MSB first.

Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 1 for the data register

format).