TLV2543C, TLV2543I

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS096B – MARCH 1995 – REVISED OCTOBER 1995

9

POST OFFICE BOX 655303

analog input, test, and power-down mode (continued)

Table 4. Power-Down-Select Address

INPUT COMMAND

VALUE SHIFTED INTO

DATA INPUT

RESULT

BINARY

HEX

Power down

1110

E

ICC ≤ 25 µA

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

This action charges all the capacitors to the input voltage.

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)

voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and

the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks

at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF –. When the voltage at the

placed in the output register and the 4096-weight capacitor is switched to REF –. When the voltage at the

summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the

4096-weight capacitor remains connected to REF + through the remainder of the successive-approximation

process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down

the line until all bits are determined. With each step of the successive-approximation process, the initial charge

is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the

bits from MSB to LSB.

SC

Threshold

Detector

Node 4096

REF –

REF+

ST

4096

VI

To Output

Latches

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF+

REF –

ST

REF –

ST

1

1

2

4

8

16

1024

2048

Figure 1. Simplified Model of the Successive-Approximation System