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TLV2543C Datasheet(PDF) 5 Page - Texas Instruments |
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TLV2543C Datasheet(HTML) 5 Page - Texas Instruments |
5 / 24 page TLV2543C, TLV2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SLAS096B – MARCH 1995 – REVISED OCTOBER 1995 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 data input (continued) Table 1. Input-Register Format INPUT DATA BYTE FUNCTION SELECT ADDRESS BITS L1 L0 LSBF BIP FUNCTION SELECT D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) Select input channel AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Select test voltage (Vref + – Vref –)/2 Vref – Vref + 1 1 1 0 1 1 1 0 0 1 0 1 Software power down 1 11 0 Output data length 8 bits 12 bits 16 bits 0 X 1 1 0 1 Output data format MSB first LSB first 0 1 Unipolar (binary) 0 Bipolar (BIP, 2s complement) 1 data input address bits The four MSBs (D7 – D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+ – Vref–. data output length The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, which is valid for the current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested. With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current conversion is output as a 12-bit serial-data stream during the next I/O cycle. The current I/O cycle must be exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle. With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial-data stream during the next I/O cycle with the four LSBs always set to 0 (pad bits). The current I/O cycle must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current I/O cycle. |
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