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TLC5905PAP Datasheet(PDF) 8 Page - Texas Instruments |
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TLC5905PAP Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 27 page  TLC5905 LED DRIVER SLLS401 – NOVEMBER 1999 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions dc characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Logic supply voltage, VCC(LOG) 4.5 5 5.5 V Supply voltage for constant current circuit, VCC(LED) 4.5 5 5.5 V Analog power supply, VCC(ANA) 4.5 5 5.5 V Voltage between VCC, V(DIFF1) V(DIFF1) = VCC(LOG) – VCC(ANA) VCC(LOG) – VCC(LED), VCC(ANA) – VCC(LED) – 0.3 0 0.3 V Voltage between GND, V(DIFF2) V(DIFF2) = GNDLOG – GND(ANA) GND(LOG) – GND(LED), GND(ANA) – GND(LED) – 0.3 0 0.3 V Voltage applied to constant current output, V(OUTn) OUT0 to OUT15 off 17 V High-level input voltage, VIH 0.8 VCC(LOG) VCC(LOG) V Low-level input voltage, VIL GNDLOG 0.2 VCC(LOG) V High-level output current, IOH VCC(LOG) = 4.5V, SOUT, BOUT, GSOUT – 1.0 mA Low level output current IOL VCC(LOG) = 4.5V, SOUT, BOUT, GSOUT 1.0 mA Low-level output current, IOL VCC(LOG) = 4.5V, XDOWN1, XDOWN2 5 mA Constant output current, IOL(C) OUT0 to OUT15 5 80 mA Operating free–air temperature range, TA – 20 85 °C ac characteristics, VCC(LOG) = VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = – 20 to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SCLK clock frequency f(SCLK) At single operation 15 MHz SCLK clock frequency, f(SCLK) At cascade operation (SOMODE = L) 10 MHz SCLK pulse duration (high or low level), tw(h)/tw(l) 20 ns GSCLK clock frequency f(GSCLK) Frequency division ratio 1/1 8 MHz GSCLK clock frequency, f(GSCLK) No GSOUT operation (see Note 2) 20 MHz GSCLK pulse duration (high or low level) t (h)/t (l) Frequency division ratio 1/1 40 ns GSCLK pulse duration (high or low level), tw(h)/tw(l) No GSOUT operation (see Note 2) 20 ns WDTRG clock frequency, f(WDT) 8 MHz WDTRG pulse duration (high or low level), tw(h)/tw(l) 40 ns XLATCH pulse duration (high), tw(h) 50 ns Rise/fall time, tr/tf 100 ns SIN – SCLK 10 BLANK – GSCLK 20 XENABLE – SCLK 15 Setup time, tsu XLATCH – SCLK 15 ns XLATCH – GSCLK 10 RSEL – SCLK 10 RSEL – XLATCH 20 SIN – SCLK 10 XENABLE – SCLK 20 Hold time, th XLATCH – SCLK 30 ns RSEL – SCLK 20 RSEL – XLATCH 20 NOTE 2: When GSCLK is operated with >8 MHz, GSOUT operation can not be assured. |
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