TLC5733A

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

9

POST OFFICE BOX 655303

correct COMPOSITE SYNC timing

The Noise Gate 1 signal provides the timing window for the COMPOSITE SYNC falling edge. After an interval

A of 867 clocks for NTSC or 1075 for PAL from the last falling edge of COMPOSITE SYNC, Noise Gate 1 signal

goes high for 43 clocks for NTSC or 61 clocks for PAL (interval B). The falling edge of the input signal to the

EXTCLP terminal can occur at any time within this window to be a valid COMPOSITE SYNC falling edge.

The Noise Gate 2 signal provides the timing window for the COMPOSITE SYNC rising edge. On the falling edge

of the horizontal sync tip, the internal logic generates Noise Gate 2 as a low signal for 58 clocks (interval C) for

both NTSC and PAL and then returns to a high active state. At this time if the input to EXTCLP is still low, it is

considered a valid COMPOSITE SYNC signal.

normal clamp pulse generation

On the rising edge of COMPOSITE SYNC, the internal logic generates an internal delay (interval D) and then

generates the internal positive clamp pulse 54 clocks wide (interval F).

clamp operation with incorrect COMPOSITE SYNC timing

noise suppression

If the input to EXTCLP goes low prior to Noise Gate 1 going high (within 43 clocks for NTSC or 61 clocks for

PAL of the normal 1H timing for the falling edge of COMPOSITE SYNC) then that input is not considered a valid

COMPOSITE SYNC and is ignored.

If the input to EXTCLP is high when Noise Gate 2 goes to the high state, the input signal is considered noise

and is ignored.

Therefore, the correct signal must be high for a maximum of 43 clocks for NTSC or 61 clocks for PAL, before

the 1H timing, to be a valid sync signal. Also, the input to EXTCLP must be at least 58 clocks wide (interval C)

to be valid.

This function of monitoring the timing eliminates spurious noise spikes from falsely synchronizing the system.

timing error of COMPOSITE SYNC

The internal counter resets to zero on the first falling edge of COMPOSITE SYNC. After that time, if there is a

missing COMPOSITE SYNC signal, then the internal logic waits an interval of 76 clocks (interval E) for NTSC

or 93 for PAL from the counter zero count and then generates an internal clamp pulse 54 clocks wide

(interval F).

This function maintains the synchronization pattern when COMPOSITE SYNC is not present.

summary of device operation with COMPOSITE SYNC

This internal timing allows the TLC5733A to correctly position the clamp pulse when an external COMPOSITE

SYNC input:

The device operation is summarized as follows for these improper external clamp conditions:

the proper time after the horizontal sync period as shown in Figure 1.

interval that the COMPOSITE SYNC input is missing.