TLC5615C, TLC5615I

10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS142C – OCTOBER 1996 – REVISED MARCH 2000

11

POST OFFICE BOX 655303

APPLICATION INFORMATION

buffer amplifier

The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-k

Ω load with a 100-pF

load capacitance. Settling time is 12.5

µs typical to within 0.5 LSB of final value.

external reference

The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,

the REFIN input resistance is 10 M

Ω and the REFIN input capacitance is typically 5 pF independent of input

code. The reference voltage determines the DAC full-scale output.

logic interface

The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves

the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic

levels.

serial clock and update rate

Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:

f

(SCLK)max +

1

t

w CH )

t

w CL

or approximately 14 MHz. The digital update rate is limited by the chip-select period, which is:

tp(CS) + 16

t

w CH )

t

w CL

) t

w CS

and is equal to 820 ns which is a 1.21 MHz update rate. However, the DAC settling time to 10 bits of 12.5

µs

limits the update rate to 80 kHz for full-scale input step transitions.