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TLC5618CD Datasheet(PDF) 7 Page - Texas Instruments |
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TLC5618CD Datasheet(HTML) 7 Page - Texas Instruments |
7 / 26 page TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref(REFIN) = 2.048 V (unless otherwise noted) (continued) digital input timing requirements MIN NOM MAX UNIT tsu(DS) Setup time, DIN before SCLK low 5 ns th(DH) Hold time, DIN valid after SCLK low 5 ns tsu(CSS) Setup time, CS low to SCLK low 5 ns tsu(CS1) Setup time, SCLK ↓ to CS ↑, external end-of-write 10 ns tsu(CS2) Setup time, SCLK ↑ to CS ↓, start of next write cycle 5 ns tw(CL) Pulse duration, SCLK low 25 ns tw(CH) Pulse duration, SCLK high 25 ns td(CS1) Delay time, CLK ↑ to data disable (TLC5618A only) 5 20 ns NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough. tsu(CSS) tw(CL) tw(CH) CS SCLK DIN tsu(DS) th(DH) D15 D14 D13 D12 D11 D0 ts DAC A/B OUT ≤ Final Value ±0.5 LSB (see Note A) Program Bits (4) DAC Data Bits (12) tsu(CS1) tsu(CS2) Figure 1. Timing Diagram for the TLC5618 |
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