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MQFL-28E-2R5S-Y-ES Datasheet(PDF) 9 Page - SynQor Worldwide Headquarters

Part # MQFL-28E-2R5S-Y-ES
Description  HIGH RELIABILITY DC-DC CONVERTER
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Manufacturer  SYNQOR [SynQor Worldwide Headquarters]
Direct Link  http://www.synqor.com
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Product # MQFL-28E-2R5S
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0005142 Rev. 2
04/30/09
Page 9
Output:
Current:
2.5V
40A
MQFL-28E-2R5S
technical Specification
BASIC OPERATION AND FEATURES
The MQFL DC/DC converter uses a two-stage power conversion
topology. The first, or regulation, stage is a buck-converter that
keeps the output voltage constant over variations in line, load,
and temperature. The second, or isolation, stage uses transform-
ers to provide the functions of input/output isolation and voltage
transformation to achieve the output voltage required.
Both the regulation and the isolation stages switch at a fixed
frequency for predictable EMI performance. The isolation stage
switches at one half the frequency of the regulation stage, but due
to the push-pull nature of this stage it creates a ripple at double its
switching frequency. As a result, both the input and the output of
the converter have a fundamental ripple frequency of about 550
kHz in the free-running mode.
Rectification of the isolation stage’s output is accomplished with
synchronous rectifiers. These devices, which are MOSFETs with a
very low resistance, dissipate far less energy than would Schottky
diodes. This is the primary reason why the MQFL converters have
such high efficiency, particularly at low output voltages.
Besides improving efficiency, the synchronous rectifiers permit
operation down to zero load current. There is no longer a need
for a minimum load, as is typical for converters that use diodes for
rectification. The synchronous rectifiers actually permit a nega-
tive load current to flow back into the converter’s output terminals
if the load is a source of short or long term energy. The MQFL
converters employ a “back-drive current limit” to keep this nega-
tive output terminal current small.
There is a control circuit on both the input and output sides of the
MQFL converter that determines the conduction state of the power
switches. These circuits communicate with each other across the
isolation barrier through a magnetically coupled device. No
opto-isolators are used.
A separate bias supply provides power to both the input and out-
put control circuits. Among other things, this bias supply permits
the converter to operate indefinitely into a short circuit and to
avoid a hiccup mode, even under a tough start-up condition.
An input under-voltage lockout feature with hysteresis is provided,
as well as an input over-voltage shutdown. There is also an
output current limit that is nearly constant as the load impedance
decreases to a short circuit (i.e., there is not fold-back or fold-
forward characteristic to the output current under this condition).
When a load fault is removed, the output voltage rises exponen-
tially to its nominal value without an overshoot.
The MQFL converter’s control circuit does not implement an output
over-voltage limit or an over-temperature shutdown.
The following sections describe the use and operation of addi-
tional control features provided by the MQFL converter.
CONTROL FEATURES
ENABLE: The MQFL converter has two enable pins. Both must
have a logic high level for the converter to be enabled. A logic
low on either pin will inhibit the converter.
The ENA1 pin (pin 4) is referenced with respect to the converter’s
input return (pin 2). The ENA2 pin (pin 12) is referenced with
respect to the converter’s output return (pin 8). This permits the
converter to be inhibited from either the input or the output side.
Regardless of which pin is used to inhibit the converter, the regu-
lation and the isolation stages are turned off. However, when
the converter is inhibited through the ENA1 pin, the bias supply
is also turned off, whereas this supply remains on when the con-
verter is inhibited through the ENA2 pin. A higher input standby
current therefore results in the latter case.
Both enable pins are internally pulled high so that an open
connection on both pins will enable the converter. Figure A
shows the equivalent circuit looking into either enable pins. It
is TTL compatible.
SHUT DOWN: The MQFL converter will shut down in response
to only four conditions: ENA1 input low, ENA2 input low, VIN
input below under-voltage lockout threshold, or VIN input above
over-voltage shutdown threshold. Following a shutdown event,
there is a startup inhibit delay which will prevent the converter
from restarting for approximately 300ms. After the 300ms delay
elapses, if the enable inputs are high and the input voltage is
within the operating range, the converter will restart. If the VIN
input is brought down to nearly 0V and back into the operating
range, there is no startup inhibit, and the output voltage will rise
according to the “Turn-On Delay, Rising Vin” specification.
REMOTE SENSE: The purpose of the remote sense pins is to
correct for the voltage drop along the conductors that connect the
converter’s output to the load. To achieve this goal, a separate
conductor should be used to connect the +SENSE pin (pin 10)
directly to the positive terminal of the load, as shown in the con-
nection diagram on Page 2. Similarly, the –SENSE pin (pin 9)
should be connected through a separate conductor to the return
terminal of the load.
NOTE: Even if remote sensing of the load voltage is not desired,
the +SENSE and the -SENSE pins must be connected to +Vout (pin
7) and OUTPUT RETURN (pin 8), respectively, to get proper regu-
lation of the converter’s output. If they are left open, the converter
will have an output voltage that is approximately 200mV higher
than its specified value. If only the +SENSE pin is left open, the
output voltage will be approximately 25mV too high.
Inside the converter, +SENSE is connected to +Vout with a resis-
tor value from 100W to 274W, depending on output voltage, and
–SENSE is connected to OUTPUT RETURN with a 10W resistor.
It is also important to note that when remote sense is used, the
voltage across the converter’s output terminals (pins 7 and 8)
will be higher than the converter’s nominal output voltage due to
resistive drops along the connecting wires. This higher voltage at
the terminals produces a greater voltage stress on the converter’s
internal components and may cause the converter to fail to deliver
the desired output voltage at the low end of the input voltage
range at the higher end of the load current and temperature
range. Please consult the factory for details.
SYNCHRONIZATION: The MQFL converter’s switching fre-
quency can be synchronized to an external frequency source
that is in the 500 kHz to 700 kHz range. A pulse train at the
desired frequency should be applied to the SYNC IN pin (pin 6)
with respect to the INPUT RETURN (pin 2). This pulse train should
have a duty cycle in the 20% to 80% range. Its low value should
be below 0.8V to be guaranteed to be interpreted as a logic low,
and its high value should be above 2.0V to be guaranteed to be
interpreted as a logic high. The transition time between the two
states should be less than 300ns.
If the MQFL converter is not to be synchronized, the SYNC IN pin
should be left open circuit. The converter will then operate in its
free-running mode at a frequency of approximately 550 kHz.
If, due to a fault, the SYNC IN pin is held in either a logic low or
logic high state continuously, the MQFL converter will revert to its
free-running frequency.
The MQFL converter also has a SYNC OUT pin (pin 5). This
output can be used to drive the SYNC IN pins of as many as ten
(10) other MQFL converters. The pulse train coming out of SYNC
OUT has a duty cycle of 50% and a frequency that matches the
switching frequency of the converter with which it is associated.
This frequency is either the free-running frequency if there is no
synchronization signal at the SYNC IN pin, or the synchroniza-
tion frequency if there is.
The SYNC OUT signal is available only when the DC input volt-
age is above approximately 12V and when the converter is not
inhibited through the ENA1 pin. An inhibit through the ENA2 pin
will not turn the SYNC OUT signal off.
NOTE: An MQFL converter that has its SYNC IN pin driven by
the SYNC OUT pin of a second MQFL converter will have its start
of its switching cycle delayed approximately 180 degrees relative
to that of the second converter.
Figure B shows the equivalent circuit looking into the SYNC IN
pin. Figure C shows the equivalent circuit looking into the
SYNC OUT pin.
Figure B:
Equivalent circuit looking into the SYNC IN pin with
respect to the IN RTN (input return) pin.
PIN 2
PIN 6
5K
5V
SYNC IN
IN RTN
TO SYNC
CIRCUITRY
5K
Figure C:
Equivalent circuit looking into SYNC OUT pin with
respect to the IN RTN (input return) pin.
FROM SYNC
CIRCUITRY
5K
5V
SYNC OUT
IN RTN
PIN 2
PIN 5
OPEN COLLECTOR
OUTPUT
CURRENT SHARE: When several MQFL converters are placed
in parallel to achieve either a higher total load power or N+1
redundancy, their SHARE pins (pin 11) should be connected
together. The voltage on this common SHARE node represents
the average current delivered by all of the paralleled converters.
Each converter monitors this average value and adjusts itself so
that its output current closely matches that of the average.
Since the SHARE pin is monitored with respect to the OUTPUT
RETURN (pin 8) by each converter, it is important to connect all of
the converters’ OUTPUT RETURN pins together through a low DC
and AC impedance. When this is done correctly, the converters
will deliver their appropriate fraction of the total load current to
within +/- 10% at full rated load.
Whether or not converters are paralleled, the voltage at the
SHARE pin could be used to monitor the approximate average
current delivered by the converter(s). A nominal voltage of 1.0V
represents zero current and a nominal voltage of 2.2V represents
the maximum rated current, with a linear relationship in between.
The internal source resistance of a converter’s SHARE pin signal
is 2.5 kW. During an input voltage fault or primary disable
event, the SHARE pin outputs a power failure warning pulse. The
SHARE pin will go to 3V for approximately 14ms as the output
voltage falls.
NOTE: Converters operating from separate input filters with
reverse polarity protection (such as the MQME-28-T filter) with
their outputs connected in parallel may exhibit hiccup operation
at light loads. Consult factory for details.
OUTPUT VOLTAGE TRIM: If desired, it is possible to increase
the MQFL converter’s output voltage above its nominal value. To
do this, use the +SENSE pin (pin 10) for this trim function instead
of for its normal remote sense function, as shown in Figure D.
In this case, a resistor connects the +SENSE pin to the –SENSE
pin (which should still be connected to the output return, either
remotely or locally). The value of the trim resistor should be
chosen according to the following equation or from Figure E:
Rtrim =
407.5
Vout – Vnom – 0.025
where:
Vnom = the converter’s nominal output voltage,
Vout = the desired output voltage (greater than Vnom), and
Rtrim is in Ohms.
As the output voltage is trimmed up, it produces a greater voltage
stress on the converter’s internal components and may cause the
converter to fail to deliver the desired output voltage at the low
end of the input voltage range at the higher end of the load
current and temperature range. Please consult the factory for
details. Factory trimmed converters are available by request.
INPUT UNDER-VOLTAGE LOCKOUT: The MQFL converter
has an under-voltage lockout feature that ensures the converter
will be off if the input voltage is too low. The threshold of
input voltage at which the converter will turn on is higher that
the threshold at which it will turn off. In addition, the MQFL
converter will not respond to a state of the input voltage unless
it has remained in that state for more than about 200µs. This
hysteresis and the delay ensure proper operation when the source
impedance is high or in a noisy environment.
INPUT OVER-VOLTAGE SHUTDOWN: The MQFL converter
also has an over-voltage feature that ensures the converter will be
off if the input voltage is too high. It also has a hysteresis and
time delay to ensure proper operation.
BACK-DRIVE CURRENT LIMIT: Converters that use MOSFETs
as synchronous rectifiers are capable of drawing a negative current
from the load if the load is a source of short- or long-term energy.
This negative current is referred to as a “back-drive current”.
Conditions where back-drive current might occur include paral-
leled converters that do not employ current sharing, or where the
current share feature does not adequately ensure sharing during
the startup or shutdown transitions. It can also occur when con-
verters having different output voltages are connected together
through either explicit or parasitic diodes that, while normally
off, become conductive during startup or shutdown. Finally, some
loads, such as motors, can return energy to their power rail. Even
a load capacitor is a source of back-drive energy for some period
of time during a shutdown transient.
To avoid any problems that might arise due to back-drive current,
the MQFL converters limit the negative current that the converter
can draw from its output terminals. The threshold for this back-
drive current limit is placed sufficiently below zero so that the con-
verter may operate properly down to zero load, but its absolute
value (see the Electrical Characteristics page) is small compared
to the converter’s rated output current.
THERMAL CONSIDERATIONS: Figure 5 shows the suggested
Power Derating Curves for this converter as a function of the
case temperature, input voltage and the maximum desired power
MOSFET junction temperature. All other components within the
converter are cooler than the hottest MOSFET.
.
The Mil-HDBK-1547A component derating guideline calls for a
maximum component temperature of 105ºC. Figure 5 therefore
has one power derating curve that ensures this limit is main-
tained. It has been SynQor’s extensive experience that reliable
long-term converter operation can be achieved with a maximum
component temperature of 125ºC. In extreme cases, a maximum
temperature of 145ºC is permissible, but not recommended for
long-term operation where high reliability is required. Derating
curves for these higher temperature limits are also included in
Figure 5. The maximum case temperature at which the converter
should be operated is 135ºC.
When the converter is mounted on a metal plate, the plate will
help to make the converter’s case bottom a uniform temperature.
How well it does so depends on the thickness of the plate and
on the thermal conductance of the interface layer (e.g. thermal
grease, thermal pad, etc.) between the case and the plate. Unless
this is done very well, it is important not to mistake the plate’s
temperature for the maximum case temperature. It is easy for
them to be as much as 5-10ºC different at full power and at high
temperatures. It is suggested that a thermocouple be attached
directly to the converter’s case through a small hole in the plate
when investigating how hot the converter is getting. Care must
also be made to ensure that there is not a large thermal resistance
between the thermocouple and the case due to whatever adhe-
sive might be used to hold the thermocouple in place.
INPUT SYSTEM INSTABILITY: This condition can occur
because any DC/DC converter appears incrementally as a
negative resistance load. A detailed application note titled
“Input System Instability” is available on the SynQor website
which provides an understanding of why this instability arises,
and shows the preferred solution for correcting it.
Figure D:
Typical connection for output voltage trimming.
28 Vdc
Load
+VIN
IN RTN
CASE
ENA 1
SYNC OUT
SYNC IN
ENA 2
SHARE
+ SNS
– SNS
OUT RTN
+VOUT
1
2
3
4
5
6
12
11
10
9
8
7
open
means
on
Rtrim
+
+
Figure E:
Output Voltage Trim Graph
2N3904
1N4148
250K
125K
82K
5.6V
TO ENABLE
CIRCUITRY
PIN 4
(or PIN 12)
PIN 2
(or PIN 8)
IN RTN
ENABLE
Figure A:
Equivalent circuit looking into either the ENA1 or ENA2
pins with respect to its corresponding return pin.


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