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TLC372Q Datasheet(PDF) 6 Page - Texas Instruments |
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TLC372Q Datasheet(HTML) 6 Page - Texas Instruments |
6 / 12 page TLC372, TLC372Q, TLC372Y LinCMOS ™ DUAL DIFFERENTIAL COMPARATORS SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS† TLC372Y UNIT PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT VIO Input offset voltage VIC = VICRmin, See Note 4 1 5 mV IIO Input offset current 1 pA IIB Input bias current 5 pA VICR Common-mode input voltage range 0 to VDD –1 V IOH High-level output current VID = 1 V, VOH = 5 V 0.1 nA VOL Low-level output voltage VID = – 1 V, IOL = 4 mA 150 400 mV IOL Low-level output current VID = – 1 V, VOL = 1.5 V 6 16 mA IDD Supply current (two comparators) VID = 1 V, No load 150 300 µA † All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement Information. NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-k Ω resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. PARAMETER MEASUREMENT INFORMATION The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. 5 V 5.1 k Ω VO Applied VIO Limit VO 5.1 k Ω 1 V –4 V – + – + (a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V Applied VIO Limit Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits |
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