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DTR-1250-SM-GB-H8-I Datasheet(PDF) 4 Page - OPLINK Communications Inc. |
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DTR-1250-SM-GB-H8-I Datasheet(HTML) 4 Page - OPLINK Communications Inc. |
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4 / 5 page  4 21737-0390, Rev. B 10-16-2003 DTR-1250-SM-GB-I Application Notes Connection of the GBIC transceiver to the host system: The GBIC’s 20-pad connector and two guide tabs connected to the transceiver’s circuit ground connect the GBIC to the host system. The two ground tabs make contact to the host circuit ground before the connector pad and discharge any possible component-damaging static electricity. Additionally, surge currents are eliminated by using a special slow start circuit and two-stage contact sequence where operational signals and grounds make contact prior to the power supply (as specified in the GBIC specification, Rev. 5.5). Electrical interface: All signal interfaces are compliant with the GBIC specification, Rev. 5.5. The high speed DATA interface is differential AC-coupled and can be directly connected to either a 5V or 3.3V SERDES IC. All low speed control and sense input/output signals are open collector TTL compatible and should be pulled up with a 4.7 - 10k Ω resistor on the host board. Loss of Signal (LOS): The Loss of Signal circuit monitors the level of the incoming optical signal and generates a logic HIGH when an insufficient photocurrent is produced. TX_FAULT: The output indicates LOW when the transmitter is operating normally, and HIGH when the transmitter or laser current is excessive. TX_FAULT is an open collector/drain output and should be pulled up with a 4.7 - 10k Ω resistor on the host board. TX_DISABLE: When the TX_DISABLE pin is at logic HIGH, the transmitter optical output is disabled (less than -35dBm). Serial Identification: The DTR-1250-SM-GB-I transceivers are compliant with Annex D (Module Definition 4) of the GBIC specification, Rev. 5.5, which defines the Serial Identification Protocol. The module definition of GBIC is indicated by the three module definition pins, MOD_DEF(0), MOD_DEF(1) and MOD_DEF(2). Module Definition 4 specifies a serial definition protocol with a two-wire I2C serial interface; upon power up, MOD_DEF(1:2) appear as NC (no connection), and MOD_DEF(0) is TTL LOW. When the host system detects this condition, it activates the serial protocol and generates the serial clock signal (SCL). The positive edge clocks data into the EEPROM segments of the GBIC that are not write protected, and the negative edge clocks data from the GBIC. The serial data signal (SDA) is for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The data transfer protocol and the details of the mandatory and vendor specific data structures are defined in Annex D of the GBIC specification, Rev. 5.5. Power supply and grounding: The power supply line should be well-filtered. All 0.1 µF power supply bypass capacitors should be as close to the GBIC transceiver module as possible. to 75 load Ω GBIC 18 2,3,8,9,11,14,17,20 19 7 +TX_DAT SCL VDD (5V) TTL LOW (internally connected to GND) SDA VCC (HOST) 15 5 46 +RX_DAT + 1 H coil or ferrite bead (<0.2 series resistance) µ Ω 10 0.1 13 12 -TX_DAT TX_DISABLE -RX_DAT 16 0.1 + 10 + 10 10 1 0.1 4.7 - 10k Ω 75 line Ω RX_LOS TX_FAULT 75 line Ω 75 line Ω 75 line Ω to 75 load Ω 4.7 - 10k Ω Example of host board schematic |
Similar Part No. - DTR-1250-SM-GB-H8-I |
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Similar Description - DTR-1250-SM-GB-H8-I |
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