TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C

HIGH-PERFORMANCE IMPACT-X

SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992

POST OFFICE BOX 655303

13

In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.

Thus, fmax without feedback +

1

(twhigh ) twlow)

or

1

(tsu ) th)

.

CLK

LOGIC

ARRAY

tsu + th

or

tw high + tw low

C1

1D

This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are

defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay

from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.

Thus, fmax with internal feedback +

1

(tsu ) tpd CLK * to * FB)

.

Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.

CLK

LOGIC

ARRAY

tsu

tpd CLK - to - FB

C1

1D